Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version
Thu Sep 21 13:38:02 2017
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Design: calculator_lcd
Constraint file:
Report level: verbose report, limited to 3 items per constraint
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Constraint: create_clock -period 1000.000000 -name clk0 [get_nets clk_c]
3451 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 983.360ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3AX CK data_state_cnt_1063__i5 (from clk_c +)
Destination: FD1P3AX D data_state_i0_i0 (to clk_c +)
Delay: 16.480ns (28.0% logic, 72.0% route), 10 logic levels.
Constraint Details:
16.480ns data_path data_state_cnt_1063__i5 to data_state_i0_i0 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 983.360ns
Path Details: data_state_cnt_1063__i5 to data_state_i0_i0
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q data_state_cnt_1063__i5 (from clk_c)
Route 33 e 2.099 data_state_cnt[5]
LUT4 --- 0.493 D to Z i2_3_lut_rep_83_4_lut
Route 9 e 1.574 n8853
LUT4 --- 0.493 D to Z i1_2_lut_3_lut_4_lut_adj_26
Route 2 e 1.141 n5858
LUT4 --- 0.493 C to Z i1_2_lut_3_lut_4_lut_adj_21
Route 1 e 0.941 n4_adj_17
LUT4 --- 0.493 B to Z i2_4_lut_adj_16
Route 3 e 1.258 n6820
LUT4 --- 0.493 C to Z i2_3_lut_4_lut_adj_14
Route 2 e 1.141 n6828
LUT4 --- 0.493 D to Z i6_4_lut
Route 13 e 1.803 n3577
LUT4 --- 0.493 D to Z i1_4_lut_adj_45
Route 1 e 0.020 n30_adj_18
MUXL5 --- 0.233 BLUT to Z i52
Route 1 e 0.941 n48_adj_24
LUT4 --- 0.493 B to Z i4456_4_lut
Route 1 e 0.941 n28_adj_6
--------
16.480 (28.0% logic, 72.0% route), 10 logic levels.
Passed: The following path meets requirements by 983.571ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3IX CK data_state_cnt_1063__i4 (from clk_c +)
Destination: FD1P3AX D data_state_i0_i0 (to clk_c +)
Delay: 16.269ns (28.4% logic, 71.6% route), 10 logic levels.
Constraint Details:
16.269ns data_path data_state_cnt_1063__i4 to data_state_i0_i0 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 983.571ns
Path Details: data_state_cnt_1063__i4 to data_state_i0_i0
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q data_state_cnt_1063__i4 (from clk_c)
Route 21 e 1.888 data_state_cnt[4]
LUT4 --- 0.493 C to Z i2_3_lut_rep_83_4_lut
Route 9 e 1.574 n8853
LUT4 --- 0.493 D to Z i1_2_lut_3_lut_4_lut_adj_26
Route 2 e 1.141 n5858
LUT4 --- 0.493 C to Z i1_2_lut_3_lut_4_lut_adj_21
Route 1 e 0.941 n4_adj_17
LUT4 --- 0.493 B to Z i2_4_lut_adj_16
Route 3 e 1.258 n6820
LUT4 --- 0.493 C to Z i2_3_lut_4_lut_adj_14
Route 2 e 1.141 n6828
LUT4 --- 0.493 D to Z i6_4_lut
Route 13 e 1.803 n3577
LUT4 --- 0.493 D to Z i1_4_lut_adj_45
Route 1 e 0.020 n30_adj_18
MUXL5 --- 0.233 BLUT to Z i52
Route 1 e 0.941 n48_adj_24
LUT4 --- 0.493 B to Z i4456_4_lut
Route 1 e 0.941 n28_adj_6
--------
16.269 (28.4% logic, 71.6% route), 10 logic levels.
Passed: The following path meets requirements by 983.598ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3IX CK data_state_cnt_1063__i6 (from clk_c +)
Destination: FD1P3AX D data_state_i0_i0 (to clk_c +)
Delay: 16.242ns (28.5% logic, 71.5% route), 10 logic levels.
Constraint Details:
16.242ns data_path data_state_cnt_1063__i6 to data_state_i0_i0 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 983.598ns
Path Details: data_state_cnt_1063__i6 to data_state_i0_i0
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q data_state_cnt_1063__i6 (from clk_c)
Route 13 e 1.861 data_state_cnt[6]
LUT4 --- 0.493 B to Z i2_3_lut_rep_83_4_lut
Route 9 e 1.574 n8853
LUT4 --- 0.493 D to Z i1_2_lut_3_lut_4_lut_adj_26
Route 2 e 1.141 n5858
LUT4 --- 0.493 C to Z i1_2_lut_3_lut_4_lut_adj_21
Route 1 e 0.941 n4_adj_17
LUT4 --- 0.493 B to Z i2_4_lut_adj_16
Route 3 e 1.258 n6820
LUT4 --- 0.493 C to Z i2_3_lut_4_lut_adj_14
Route 2 e 1.141 n6828
LUT4 --- 0.493 D to Z i6_4_lut
Route 13 e 1.803 n3577
LUT4 --- 0.493 D to Z i1_4_lut_adj_45
Route 1 e 0.020 n30_adj_18
MUXL5 --- 0.233 BLUT to Z i52
Route 1 e 0.941 n48_adj_24
LUT4 --- 0.493 B to Z i4456_4_lut
Route 1 e 0.941 n28_adj_6
--------
16.242 (28.5% logic, 71.5% route), 10 logic levels.
Report: 16.640 ns is the maximum delay for this constraint.
Timing Report Summary
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Constraint | Constraint| Actual|Levels
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| | |
create_clock -period 1000.000000 -name | | |
clk0 [get_nets clk_c] | 1000.000 ns| 16.640 ns| 10
| | |
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All constraints were met.
Timing summary:
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Timing errors: 0 Score: 0
Constraints cover 4572 paths, 357 nets, and 1059 connections (98.2% coverage)
Peak memory: 75112448 bytes, TRCE: 2555904 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs